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HD64F3052BTE Datasheet(PDF) 5 Page - Renesas Technology Corp |
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HD64F3052BTE Datasheet(HTML) 5 Page - Renesas Technology Corp |
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5 / 845 page  Rev. 3.00 Mar 21, 2006 page v of xxviii Preface The H8/3052BF is a group of high-performance microcontrollers that integrate system supporting functions together with an H8/300H CPU core. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space. The on-chip supporting functions include ROM, RAM, a 16-bit integrated timer unit (ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller (DMAC), a refresh controller, and other facilities. Of the two SCI channels, one has been expanded to support the ISO/IEC7816-3 smart card interface. Functions have also been added to reduce power consumption in battery-powered applications: individual modules can be placed in standby, and the frequency of the system clock supplied to the chip can be divided down under software control. The address space is divided into eight areas. The data bus width and access cycle length can be selected independently in each area, simplifying the connection of different types of memory. Seven operating modes (modes 1 to 7) are provided, offering a choice of data bus width and address space size. With these features, the H8/3052BF can be used to implement compact, high-performance systems easily. The H8/3052BF has an F-ZTAT * version with on-chip flash memory that can be programmed on-board. These versions enable users to respond quickly and flexibly to changing application specifications. This manual describes the H8/3052BF hardware. For details of the instruction set, refer to the H8/300H Series Software Manual. Note: * F-ZTAT (Flexible–Zero Turn Around Time) is a trademark of Renesas Technology Corp. |
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