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HD6433048VF Datasheet(PDF) 10 Page - Renesas Technology Corp |
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HD6433048VF Datasheet(HTML) 10 Page - Renesas Technology Corp |
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10 / 905 page  Rev. 7.00 Sep 21, 2005 page x of xxiv Item Page Revision (See Manual for Details) 19.5.6 Erasing Flowchart and Sample Program Flowchart for Erasing Multiple Blocks Figure 19.12 Multiple-Block Erase Flowchart 616 Figure amended Enable watchdog timer Wait initial value setting x = 6.25 ms *2 Select erase mode (E bit = 1 in FLMCR) Wait (x) ms Clear E bit Disable watchdog timer Select erase-verify mode (EV bit = 1 in FLMCR) Wait (tVS1) µs Set top address of block as verify address Dummy write to verify address (flash memory latches address) 3 * Erase-verify next block Verify *4 (read memory) Last address in block? Address + 1 → address Clear EBR bit of erase-verified block All erased blocks verified? Clear EV bit All blocks erased? (EBR1 = EBR2 = 0?) End of erase n ≥ N? Erase error n + 1 → n No No Yes Yes No No Yes No Yes No good OK Erasing ends All erased blocks verified? Erase-verify next block Yes No Yes V E PP Clear bit Clear erase block registers (clear bits of blocks to be erased to 0) n ≥ 4? Wait (tVS2) µs V E PP Clear bit Double the erase time (x × 2 → x) 5. tVS1: 4 µs z: 5 to 10 µs tVS2: 2 µs N: 602 6. The erase time x is successively incremented by the initial set value × 2n–1 (n = 1, 2, 3, 4). An initial value of 10 ms or less should be set, and the time for one erasure should be 50 ms or less. *5 *5 *6 |
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