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H838703 Datasheet(PDF) 10 Page - Renesas Technology Corp |
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H838703 Datasheet(HTML) 10 Page - Renesas Technology Corp |
10 / 402 page Rev. 1.00 Dec. 13, 2007 Page x of xviii Contents Section 1 Overview ............................................................................................... 1 1.1 Features................................................................................................................................. 1 1.1.1 Application ........................................................................................................... 1 1.1.2 Overview of Specifications................................................................................... 2 1.2 List of Products..................................................................................................................... 5 1.3 Block Diagram...................................................................................................................... 7 1.4 Pin Assignment..................................................................................................................... 8 1.5 Pin Functions ........................................................................................................................ 9 Section 2 CPU ..................................................................................................... 13 2.1 Address Space and Memory Map ....................................................................................... 15 2.2 Register Configuration........................................................................................................ 21 2.2.1 General Registers................................................................................................ 22 2.2.2 Program Counter (PC) ........................................................................................ 23 2.2.3 Condition-Code Register (CCR)......................................................................... 23 2.3 Data Formats....................................................................................................................... 25 2.3.1 General Register Data Formats........................................................................... 25 2.3.2 Memory Data Formats ........................................................................................ 27 2.4 Instruction Set..................................................................................................................... 28 2.4.1 Table of Instructions Classified by Function ...................................................... 28 2.4.2 Basic Instruction Formats ................................................................................... 38 2.5 Addressing Modes and Effective Address Calculation....................................................... 39 2.5.1 Addressing Modes .............................................................................................. 39 2.5.2 Effective Address Calculation ............................................................................ 43 2.6 Basic Bus Cycle .................................................................................................................. 45 2.6.1 Access to On-Chip Memory (RAM, ROM)........................................................ 45 2.6.2 On-Chip Peripheral Modules .............................................................................. 46 2.7 CPU States .......................................................................................................................... 47 2.8 Usage Notes ........................................................................................................................ 48 2.8.1 Notes on Data Access to Empty Areas ............................................................... 48 2.8.2 EEPMOV Instruction.......................................................................................... 48 2.8.3 Bit-Manipulation Instruction .............................................................................. 49 Section 3 Exception Handling ............................................................................. 55 3.1 Exception Sources and Vector Address .............................................................................. 58 3.2 Register Descriptions.......................................................................................................... 59 |
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