HD64F3068TE datasheet(10/935 Pages) RENESAS

Part #	HD64F3068TE

Description	Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

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Manufacturer	RENESAS [Renesas Technology Corp]

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10 / 935 page

Rev. 3.00 Sep 14, 2005 page x of xxii

6.2.9

Refresh Timer Control/Status Register (RTMCSR) ............................................ 135

6.2.10 Refresh Timer Counter (RTCNT)........................................................................ 136

6.2.11 Refresh Time Constant Register (RTCOR) ......................................................... 137

6.2.12 Address Control Register (ADRCR) ................................................................... 138

6.3

Operation .......................................................................................................................... 139

6.3.1

Area Division....................................................................................................... 139

6.3.2

Bus Specifications ............................................................................................... 141

6.3.3

Memory Interfaces............................................................................................... 142

6.3.4

Chip Select Signals .............................................................................................. 143

6.3.5

Address Output Method....................................................................................... 144

6.4

Basic Bus Interface ........................................................................................................... 146

6.4.1

Overview.............................................................................................................. 146

6.4.2

Data Size and Data Alignment............................................................................. 146

6.4.3

Valid Strobes ...................................................................................................... 147

6.4.4

Memory Areas ..................................................................................................... 148

6.4.5

Basic Bus Control Signal Timing ........................................................................ 150

6.4.6

Wait Control ........................................................................................................ 157

6.5

DRAM Interface ............................................................................................................... 159

6.5.1

Overview.............................................................................................................. 159

6.5.2

DRAM Space and

RAS Output Pin Settings ....................................................... 159

6.5.3

Address Multiplexing .......................................................................................... 160

6.5.4

Data Bus .............................................................................................................. 161

6.5.5

Pins Used for DRAM Interface ........................................................................... 162

6.5.6

Basic Timing........................................................................................................ 162

6.5.7

Precharge State Control ....................................................................................... 164

6.5.8

Wait Control ........................................................................................................ 165

6.5.9

Byte Access Control and

CAS Output Pin .......................................................... 166

6.5.10 Burst Operation.................................................................................................... 168

6.5.11 Refresh Control.................................................................................................... 174

6.5.12 Examples of Use .................................................................................................. 178

6.5.13 Usage Notes ......................................................................................................... 183

6.6

Interval Timer ................................................................................................................... 186

6.6.1

Operation ............................................................................................................. 186

6.7

Interrupt Sources............................................................................................................... 192

6.8

Burst ROM Interface ........................................................................................................ 192

6.8.1

Overview.............................................................................................................. 192

6.8.2

Basic Timing........................................................................................................ 192

6.8.3

Wait Control ........................................................................................................ 193

6.9

Idle Cycle.......................................................................................................................... 194

6.9.1

Operation ............................................................................................................. 194

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