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ISO35 Datasheet(PDF) 11 Page - Renesas Technology Corp |
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ISO35 Datasheet(HTML) 11 Page - Renesas Technology Corp |
11 / 20 page IEC SAFETY LIMITING VALUES THERMAL CHARACTERISTICS 0 25 50 75 100 125 150 175 200 225 250 275 300 0 50 100 150 200 T -CaseTemperature-°C C V at3.6V CC1,2 ISO15 ISO35 www.ti.com................................................................................................................................................................ SLOS580B – MAY 2008 – REVISED JULY 2008 Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT θ JA = 212°C/W, VI = 5.5 V, IS Safety input, output, or supply current DW-16 210 mA TJ = 170°C, TA = 25°C TS Maximum case temperature DW-16 150 °C The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Characteristics table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages and is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Low-K Thermal Resistance(1) 168 θ JA Junction-to-Air °C/W High-K Thermal Resistance 96.1 θ JB Junction-to-Board Thermal Resistance 61 °C/W θ JC Junction-to-Case Thermal Resistance 48 °C/W VCC1 = VCC2 = 5.25 V, TJ = 150°C, CL = 15 pF, PD Device Power Dissipation 220 mW Input a 20 MHz 50% duty cycle square wave (1) Tested in accordance with the Low-K or High-K thermal metric defintions of EIA/JESD51-3 for leaded surface mount packages. Figure 14. DW-16 θ JC Thermal Derating Curve per IEC 60747-5-2 Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): ISO15 ISO35 |
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