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R4S2454 Datasheet(PDF) 10 Page - Renesas Technology Corp |
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R4S2454 Datasheet(HTML) 10 Page - Renesas Technology Corp |
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10 / 1376 page  Rev. 1.00 Sep. 19, 2008 Page x of xxx 2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)................. 71 2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn.................................................................. 71 2.7.5 Absolute Address—@aa:8 /@aa:16 / @aa:24 /@aa:32.......................................... 71 2.7.6 Immediate—#xx:8 / #xx:16/ #xx:32 ....................................................................... 72 2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC) ...................................... 72 2.7.8 Memory Indirect—@@aa:8 ................................................................................... 72 2.7.9 Effective Address Calculation ................................................................................ 74 2.8 Processing States.................................................................................................................. 76 2.9 Usage Note........................................................................................................................... 78 2.9.1 Usage Notes on Bit-wise Operation Instructions .................................................... 78 Section 3 MCU Operating Modes ....................................................................... 79 3.1 Operating Mode Selection ................................................................................................... 79 3.2 Register Descriptions ...........................................................................................................80 3.2.1 Mode Control Register (MDCR) ............................................................................ 80 3.2.2 System Control Register (SYSCR) ......................................................................... 81 3.3 Operating Mode Descriptions .............................................................................................. 83 3.3.1 Mode 1 .................................................................................................................... 83 3.3.2 Mode 2 .................................................................................................................... 83 3.3.3 Mode 3 .................................................................................................................... 83 3.3.4 Mode 4 .................................................................................................................... 84 3.3.5 Mode 7 .................................................................................................................... 84 3.3.6 Pin Functions .......................................................................................................... 85 3.4 Memory Map in Each Operating Mode ............................................................................... 86 Section 4 Exception Handling ............................................................................. 93 4.1 Exception Handling Types and Priority............................................................................... 93 4.2 Exception Sources and Exception Vector Table .................................................................. 94 4.3 Reset .................................................................................................................................... 96 4.3.1 Reset Exception Handling ...................................................................................... 96 4.3.2 Interrupts after Reset............................................................................................... 98 4.3.3 On-Chip Peripheral Functions after Reset Release ................................................. 98 4.4 Trace Exception Handling ................................................................................................... 99 4.5 Interrupt Exception Handling ............................................................................................ 100 4.6 Trap Instruction Exception Handling................................................................................. 101 4.7 Illegal Instruction Exception Handling .............................................................................. 102 4.8 Stack Status after Exception Handling............................................................................... 103 4.9 Usage Note......................................................................................................................... 104 |
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