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H8S2607 Datasheet(PDF) 11 Page - Renesas Technology Corp |
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H8S2607 Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 710 page  Rev. 1.00 Jan. 29, 2008 Page xi of xl 5.3.2 IRQ Enable Register (IER) ..................................................................................... 76 5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL)........................................ 77 5.3.4 IRQ Status Register (ISR)....................................................................................... 79 5.4 Interrupt Sources.................................................................................................................. 80 5.4.1 External Interrupts .................................................................................................. 80 5.4.2 Internal Interrupts ................................................................................................... 81 5.5 Interrupt Exception Handling Vector Table......................................................................... 81 5.6 Interrupt Control Modes and Interrupt Operation ................................................................ 85 5.6.1 Interrupt Control Mode 0 ........................................................................................ 85 5.6.2 Interrupt Control Mode 2 ........................................................................................ 87 5.6.3 Interrupt Exception Handling Sequence ................................................................. 89 5.6.4 Interrupt Response Times ....................................................................................... 91 5.6.5 DTC Activation by Interrupt................................................................................... 92 5.7 Usage Notes ......................................................................................................................... 93 5.7.1 Conflict between Interrupt Generation and Disabling ............................................ 93 5.7.2 Instructions that Disable Interrupts ......................................................................... 94 5.7.3 When Interrupts Are Disabled ................................................................................ 94 5.7.4 Interrupts during Execution of EEPMOV Instruction ............................................ 94 Section 6 PC Break Controller (PBC) .................................................................95 6.1 Features................................................................................................................................ 95 6.2 Register Descriptions ...........................................................................................................96 6.2.1 Break Address Register A (BARA) ........................................................................ 96 6.2.2 Break Address Register B (BARB) ........................................................................ 97 6.2.3 Break Control Register A (BCRA) ......................................................................... 97 6.2.4 Break Control Register B (BCRB) ......................................................................... 98 6.3 Operation ............................................................................................................................. 98 6.3.1 PC Break Interrupt Due to Instruction Fetch .......................................................... 98 6.3.2 PC Break Interrupt Due to Data Access.................................................................. 99 6.3.3 PC Break Operation at Consecutive Data Transfer................................................. 99 6.3.4 Operation in Transitions to Power-Down Modes ................................................... 99 6.3.5 When Instruction Execution Is Delayed by One State.......................................... 101 6.4 Usage Notes ....................................................................................................................... 102 6.4.1 Module Stop Mode Setting ................................................................................... 102 6.4.2 PC Break Interrupts .............................................................................................. 102 6.4.3 CMFA and CMFB ................................................................................................ 102 6.4.4 PC Break Interrupt when DTC Is Bus Master ...................................................... 102 6.4.5 PC Break Set for Instruction Fetch at Address Following BSR, JSR, JMP, TRAPA, RTE, or RTS Instruction ........................... 102 6.4.6 I Bit Set by LDC, ANDC, ORC, or XORC Instruction ........................................ 102 |
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