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HD64F2280B Datasheet(PDF) 9 Page - Renesas Technology Corp |
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HD64F2280B Datasheet(HTML) 9 Page - Renesas Technology Corp |
9 / 615 page Rev. 3.00 Sep 26, 2006 page ix of xxxii 5.6.1 Interrupt Control Mode 0 ..................................................................................... 85 5.6.2 Interrupt Control Mode 2 ..................................................................................... 87 5.6.3 Interrupt Exception Handling Sequence .............................................................. 88 5.6.4 Interrupt Response Times .................................................................................... 90 5.7 Usage Notes ...................................................................................................................... 91 5.7.1 Contention between Interrupt Generation and Disabling..................................... 91 5.7.2 Instructions that Disable Interrupts ...................................................................... 92 5.7.3 When Interrupts Are Disabled ............................................................................. 92 5.7.4 Interrupts during Execution of EEPMOV Instruction.......................................... 93 5.7.5 IRQ Interrupts ...................................................................................................... 93 Section 6 Bus Controller ................................................................................................... 95 6.1 Basic Timing ..................................................................................................................... 95 6.1.1 On-Chip Memory Access Timing (ROM, RAM) ................................................ 95 6.1.2 On-Chip Peripheral Module Access Timing........................................................ 96 6.1.3 On-Chip HCAN Module Access Timing ............................................................. 97 6.1.4 On-Chip PWM, LCD, Ports H and J Module Access Timing ............................. 98 Section 7 I/O Ports .............................................................................................................. 99 7.1 Port 1................................................................................................................................. 106 7.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 106 7.1.2 Port 1 Data Register (P1DR)................................................................................ 107 7.1.3 Port 1 Register (PORT1)...................................................................................... 107 7.1.4 Pin Functions ....................................................................................................... 108 7.2 Port 3................................................................................................................................. 116 7.2.1 Port 3 Data Direction Register (P3DDR)............................................................. 116 7.2.2 Port 3 Data Register (P3DR)................................................................................ 117 7.2.3 Port 3 Register (PORT3)...................................................................................... 117 7.2.4 Port 3 Open-Drain Control Register (P3ODR) .................................................... 118 7.2.5 Pin Functions ....................................................................................................... 119 7.3 Port 4................................................................................................................................. 121 7.3.1 Port 4 Register (PORT4)...................................................................................... 121 7.3.2 Pin Functions ....................................................................................................... 122 7.4 Port A ................................................................................................................................ 123 7.4.1 Port A Data Direction Register (PADDR) ........................................................... 123 7.4.2 Port A Data Register (PADR) .............................................................................. 124 7.4.3 Port A Register (PORTA) .................................................................................... 124 7.4.4 Port A Open Drain Control Register (PAODR)................................................... 125 7.4.5 H8S/2282 Group and H8S/2280 Group (HD64F2280B) Pin Functions .............. 125 7.4.6 H8S/2280 Group (HD64F2280RB) Pin Functions .............................................. 126 7.5 Port B ................................................................................................................................ 127 |
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