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HD6432192 Datasheet(PDF) 11 Page - Renesas Technology Corp |
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HD6432192 Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 1078 page  Rev.3.00 Jan. 10, 2007 page xi of xxxvi REJ09B0328-0300 Item Page Revision (See Manual for Details) 28.13.6 Operation Figure 28.50 Example of CTLM Switchover Timing (When Phase Control Is Performed by REF30P and DVCFG2 in REC Mode) 751 Figure 28.50 amended (Before) PDCR3 → (After) PCDR3 Figure 28.51 Example of CTLM Switchover Timing (When Phase Control Is Performed by CREF and DVCFG2 in REC Mode) 752 Figure 28.51 amended Ta is the interval calculated from RCDR3. … 28.18.9 CTL Output Section Table 28.21 REC-CTL Duty Register and CTL Outputs 762 Table 28.21 amended (Before) 65.5 ±0.5% → (After) 62.5 ±0.5% 28.15.6 Noise Detection 790 (1) Example of Setting Description amended ∴HPWR3 - 0 = H'B 29.2.7 Flash Memory Characteristics Table 29.12 Flash Memory Characteristics (Preliminary) 824 Table 29.12 amended Item Symbol Min Typ Max Unit Test Conditions Erasing time* 1*3*5 tE 100 1200 ms/ block Reprogramming count NWEC x 100 *7 10000 *8 — Times Data retention time* 9 tDRP 10 — —— — Years Wait time after SWE-bit setting* 1 10 μs At Programming 825 Notes 7 to 9 added Notes: 7. Minimum number of times for which all characteristics are guaranteed after rewriting (Guarantee range is 1 to minimum value). 8. Reference value for 25°C (as a guideline, rewriting should normally function up to this value). 9. Data retention characteristic when rewriting is performed within the specification range, including the minimum value. |
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