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H8S2194 Datasheet(PDF) 5 Page - Renesas Technology Corp |
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H8S2194 Datasheet(HTML) 5 Page - Renesas Technology Corp |
5 / 1078 page Rev.3.00 Jan. 10, 2007 page v of xxxvi REJ09B0328-0300 Main Revisions for This Edition Item Page Revision (See Manual for Details) All — • Notification of change in company name amended (Before) Hitachi, Ltd. → (After) Renesas Technology Corp. • Product naming convention amended (Before) H8S/2194 Series → (After) H8S/2194 Group (Before) H8S/2194C Series → (After) H8S/2194C Group 2.8.1 Overview Figure 2.15 State Transitions 54 Figure 2.15 amended RES = High SLEEP instruction with LSON = 0, TMA3 = 0, SSBY = 0 4.2.3 Timer Register A (TMA) 79 Table amended • Timer A counts φ-based prescalar (PSS) divided clock pulses • Timer A counts φw-based prescalar (PSW) divided clock pulses 4.6.1 Standby Mode 83 Description amended … RAM as well as functions of the SCI1, timer X1 … 4.6.2 Clearing Standby Mode 83 (1) Clearing with an Interrupt ... in bits STS2 to STS0 in SBYCR, stable clocks are supplied ... 6.2.6 Port Mode Register (PMR1) 106 Table amended P1n/ IRQn pin functions as the IRQn input pin 7.2.5 Register Configuration Table 7.3 Flash Memory Registers 132 Access size description deleted from table 7.3 7.4.1 Boot Mode 143 (1) Automatic SCI Bit Rate Adjustment Description amended … bit rate should be set to (4800, or 9600) bps. … 8.4.1 Boot Mode 191 (1) Automatic SCI Bit Rate Adjustment Description amended … bit rate should be set to (4800, or 9600) bps. … 8.5 Programming/Erasing Flash Memory 195 Description amended … PSU2, ESU2, P2, E2, PV2, and EV2 bits in FLMCR2. … |
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