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AFE5805 Datasheet(PDF) 10 Page - Texas Instruments |
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AFE5805 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 51 page  AFE5805 SBOS421C – MARCH 2008 – REVISED OCTOBER 2008................................................................................................................................................. www.ti.com Table 1. TERMINAL FUNCTIONS PIN NO. PIN NAME FUNCTION DESCRIPTION H7 CS Input Chip select for serial interface; active low H1 ADS_PD Input Power-down pin for ADS; active high. See the Power-Down Modes section for more information. H9 ADS_RESET Input RESET input for ADS; active low H6 SCLK Input Serial clock input for serial interface H8 SDATA Input Serial data input for serial interface J2, L2, K7, J7, AVDD1 POWER 3.3V analog supply for ADS K3, L8, K5, K6 L3, M3, L4, M4, L5, M5, L6, M6, AVSS1 GND Analog ground for ADS L7, M7, J1 P5, N6, N7 LVDD POWER 1.8V digital supply for ADS N3, N4, N5, R5 LVSS GND Digital ground for ADS C5, D5 DVDD POWER 3.3V digital supply for the VCA; connect to the 3.3V analog supply (AVDD2). C2, C8, G2, G8 AVDD2 POWER 3.3V analog supply for VCA E2, E8 AVDD_5V POWER 5V supply for VCA C3, D3, C4, D4, E4, F4, G4, E5, F5, G5, C6, D6, AVSS2 GND Analog ground for VCA E6, F6, G6, C7, D7, J4, J5, J6 K1 CLKM Input Negative clock input for ADS (connect to Ground in single-ended clock mode) L1 CLKP Input Positive clock input for ADS K8 CM Input/Output 1.5V common-mode I/O for ADS. Becomes input pin in one of the external reference modes. C9 CW0 Output CW output 0 D9 CW1 Output CW output 1 E9 CW2 Output CW output 2 F9 CW3 Output CW output 3 G9 CW4 Output CW output 4 G1 CW5 Output CW output 5 F1 CW6 Output CW output 6 E1 CW7 Output CW output 7 D1 CW8 Output CW output 8 C1 CW9 Output CW output 9 L9 EN_SM Input Enables access to the VCA register. Active high. Connect permanently to 3.3V (AVDD1). N8 FCLKM Output LVDS frame clock (negative output) N9 FCLKP Output LVDS frame clock (positive output) A1 IN1 Input LNA input Channel 1 A2 IN2 Input LNA input Channel 2 A3 IN3 Input LNA input Channel 3 A4 IN4 Input LNA input Channel 4 A9 IN5 Input LNA input Channel 5 A8 IN6 Input LNA input Channel 6 A7 IN7 Input LNA input Channel 7 A6 IN8 Input LNA input Channel 8 J3 INT/EXT Input Internal/ external reference mode select for ADS; internal = high (internal pull-up resistor) K9 ISET Input Current bias pin for ADS. Requires 56k Ω to ground. N2 LCLKM Output LVDS bit clock (6x); negative output N1 LCLKP Output LVDS bit clock (6x); positive output R4 OUT1M Output LVDS data output (negative), Channel 1 P4 OUT1P Output LVDS data output (positive), Channel 1 R3 OUT2M Output LVDS data output (negative), Channel 2 P3 OUT2P Output LVDS data output (positive), Channel 2 R2 OUT3M Output LVDS data output (negative), Channel 3 10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): AFE5805 |
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