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R5F61638L Datasheet(PDF) 11 Page - Renesas Technology Corp |
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R5F61638L Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 1164 page  Rev. 2.00 Sep. 10, 2008 Page xi of xxviii 4.3 Register Descriptions .......................................................................................................... 86 4.3.1 Reset Status Register (RSTSR)........................................................................... 86 4.3.2 Reset Control/Status Register (RSTCSR)........................................................... 88 4.4 Pin Reset ............................................................................................................................. 89 4.5 Power-on Reset (POR) (H8SX/1638L Group) ................................................................... 89 4.6 Power Supply Monitoring Reset (H8SX1638L Group) ...................................................... 90 4.7 Deep Software Standby Reset............................................................................................. 91 4.8 Watchdog Timer Reset ....................................................................................................... 91 4.9 Determination of Reset Generation Source......................................................................... 92 Section 5 Voltage Detection Circuit (LVD) ........................................................93 5.1 Features............................................................................................................................... 93 5.2 Register Descriptions .......................................................................................................... 94 5.2.1 Voltage Detection Control Register (LVDCR)................................................... 94 5.2.2 Reset Status Register (RSTSR)........................................................................... 95 5.3 Voltage Detection Circuit ................................................................................................... 97 5.3.1 Voltage Monitoring Reset................................................................................... 97 5.3.2 Voltage Monitoring Interrupt.............................................................................. 98 5.3.3 Release from Deep Software Standby Mode by the Voltage-Detection Circuit ............................................................................................................... 100 5.3.4 Voltage Monitor................................................................................................ 100 Section 6 Exception Handling ...........................................................................101 6.1 Exception Handling Types and Priority............................................................................ 101 6.2 Exception Sources and Exception Handling Vector Table ............................................... 102 6.3 Reset ................................................................................................................................. 104 6.3.1 Reset Exception Handling................................................................................. 104 6.3.2 Interrupts after Reset......................................................................................... 105 6.3.3 On-Chip Peripheral Functions after Reset Release ........................................... 105 6.4 Traces................................................................................................................................ 107 6.5 Address Error.................................................................................................................... 108 6.5.1 Address Error Source........................................................................................ 108 6.5.2 Address Error Exception Handling ................................................................... 109 6.6 Interrupts........................................................................................................................... 110 6.6.1 Interrupt Sources............................................................................................... 110 6.6.2 Interrupt Exception Handling ........................................................................... 111 6.7 Instruction Exception Handling ........................................................................................ 111 6.7.1 Trap Instruction................................................................................................. 111 6.7.2 Sleep Instruction Exception Handling .............................................................. 112 6.7.3 Exception Handling by Illegal Instruction ........................................................ 113 |
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