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HD64F2362 Datasheet(PDF) 10 Page - Renesas Technology Corp |
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HD64F2362 Datasheet(HTML) 10 Page - Renesas Technology Corp |
10 / 1037 page Rev. 5.00 Aug 02, 2006 page x of liv Item Page Revision (See Manual for Details) 14.3.9 Bit Rate Register (BRR) Table 14.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) 567 Note * amended Note: * Supported only by the H8S/2368 0.18 µm F-ZTAT Group. Table 14.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) 568 Note * amended Note: * Supported only by the H8S/2368 0.18 µm F-ZTAT Group. Table 14.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) 569 Note 1 amended Note: 1. Supported only by the H8S/2368 0.18 µm F-ZTAT Group. Table 14.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) 570 Note * amended Note: * Supported only by the H8S/2368 0.18 µm F-ZTAT Group. Table 14.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (when n = 0 and S = 372) 571 Note * amended Note: * Supported only by the H8S/2368 0.18 µm F-ZTAT Group. Table 14.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372) 572 Note * amended Note: * Supported only by the H8S/2368 0.18 µm F-ZTAT Group. 14.8 IrDA Operation Table 14.12 Settings of Bits IrCKS2 to IrCKS0 618 Note * amended Note: * Supported only by the H8S/2368 0.18 µm F-ZTAT Group. 15.3.1 I 2C Bus Control Register A (ICCRA) Table 15.2 Transfer Rate 634 Note 1 amended Note: 1. Supported only by the H8S/2368 0.18 µm F-ZTAT Group. |
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