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HD64F36012 Datasheet(PDF) 10 Page - Renesas Technology Corp |
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HD64F36012 Datasheet(HTML) 10 Page - Renesas Technology Corp |
10 / 384 page Rev. 4.00 Sep. 23, 2005 Page x of xxvi 3.2.4 Interrupt Flag Register 1 (IRR1)............................................................................. 50 3.2.5 Wakeup Interrupt Flag Register (IWPR) ................................................................ 51 3.3 Reset Exception Handling.................................................................................................... 52 3.4 Interrupt Exception Handling .............................................................................................. 53 3.4.1 External Interrupts .................................................................................................. 53 3.4.2 Internal Interrupts ................................................................................................... 54 3.4.3 Interrupt Handling Sequence .................................................................................. 55 3.4.4 Interrupt Response Time......................................................................................... 56 3.5 Usage Notes ......................................................................................................................... 58 3.5.1 Interrupts after Reset............................................................................................... 58 3.5.2 Notes on Stack Area Use ........................................................................................ 58 3.5.3 Notes on Rewriting Port Mode Registers ............................................................... 58 Section 4 Address Break ..................................................................................... 59 4.1 Register Descriptions ...........................................................................................................59 4.1.1 Address Break Control Register (ABRKCR) ......................................................... 60 4.1.2 Address Break Status Register (ABRKSR) ............................................................ 61 4.1.3 Break Address Registers (BARH, BARL).............................................................. 62 4.1.4 Break Data Registers (BDRH, BDRL) ................................................................... 62 4.2 Operation ............................................................................................................................. 62 Section 5 Clock Pulse Generators ....................................................................... 65 5.1 System Clock Generator ...................................................................................................... 65 5.1.1 Connecting Crystal Resonator ................................................................................ 66 5.1.2 Connecting Ceramic Resonator .............................................................................. 66 5.1.3 External Clock Input Method ................................................................................. 67 5.2 Prescalers ............................................................................................................................. 67 5.2.1 Prescaler S .............................................................................................................. 67 5.3 Usage Notes ......................................................................................................................... 67 5.3.1 Note on Resonators................................................................................................. 67 5.3.2 Notes on Board Design ........................................................................................... 68 Section 6 Power-Down Modes ............................................................................ 69 6.1 Register Descriptions ...........................................................................................................69 6.1.1 System Control Register 1 (SYSCR1) .................................................................... 70 6.1.2 System Control Register 2 (SYSCR2) .................................................................... 71 6.1.3 Module Standby Control Register 1 (MSTCR1) .................................................... 72 6.1.4 Module Standby Control Register 2 (MSTCR2) .................................................... 72 6.2 Mode Transitions and States of LSI..................................................................................... 73 6.2.1 Sleep Mode ............................................................................................................. 75 |
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