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SH7606 Datasheet(PDF) 9 Page - Renesas Technology Corp |
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SH7606 Datasheet(HTML) 9 Page - Renesas Technology Corp |
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9 / 532 page  Rev. 4.00 Sep. 13, 2007 Page ix of xxvi 3.3.3 Write Access ........................................................................................................... 57 3.3.4 Write-Back Buffer .................................................................................................. 57 3.3.5 Coherency of Cache and External Memory ............................................................ 58 3.4 Memory-Mapped Cache ...................................................................................................... 58 3.4.1 Address Array ......................................................................................................... 58 3.4.2 Data Array .............................................................................................................. 59 3.4.3 Usage Examples...................................................................................................... 61 Section 4 U Memory............................................................................................63 4.1 Features................................................................................................................................ 63 Section 5 Exception Handling .............................................................................65 5.1 Overview.............................................................................................................................. 65 5.1.1 Types of Exception Handling and Priority.............................................................. 65 5.1.2 Exception Handling Operations .............................................................................. 66 5.1.3 Exception Handling Vector Table........................................................................... 67 5.2 Resets ................................................................................................................................... 69 5.2.1 Types of Resets....................................................................................................... 69 5.2.2 Power-On Reset ...................................................................................................... 69 5.2.3 H-UDI Reset ........................................................................................................... 70 5.3 Address Errors ..................................................................................................................... 71 5.3.1 Address Error Sources ............................................................................................ 71 5.3.2 Address Error Exception Source............................................................................. 71 5.4 Interrupts.............................................................................................................................. 72 5.4.1 Interrupt Sources..................................................................................................... 72 5.4.2 Interrupt Priority ..................................................................................................... 72 5.4.3 Interrupt Exception Handling ................................................................................. 73 5.5 Exceptions Triggered by Instructions .................................................................................. 74 5.5.1 Types of Exceptions Triggered by Instructions ...................................................... 74 5.5.2 Trap Instructions ..................................................................................................... 74 5.5.3 Illegal Slot Instructions ........................................................................................... 75 5.5.4 General Illegal Instructions..................................................................................... 75 5.6 Cases When Exceptions are Accepted ................................................................................. 76 5.7 Stack States after Exception Handling Ends ........................................................................ 77 5.8 Usage Notes ......................................................................................................................... 79 5.8.1 Value of Stack Pointer (SP) .................................................................................... 79 5.8.2 Value of Vector Base Register (VBR) .................................................................... 79 5.8.3 Address Errors Caused by Stacking for Address Error Exception Handling .......... 79 5.8.4 Notes on Slot Illegal Instruction Exception Handling ............................................ 79 |
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