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HD6432647 Datasheet(PDF) 10 Page - Renesas Technology Corp |
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HD6432647 Datasheet(HTML) 10 Page - Renesas Technology Corp |
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10 / 1165 page  Rev. 5.00 Sep 22, 2005 page x of xxvi 2.8.6 Power-Down State ............................................................................................... 69 2.9 Basic Timing..................................................................................................................... 70 2.9.1 Overview ............................................................................................................. 70 2.9.2 On-Chip Memory (ROM, RAM)......................................................................... 70 2.9.3 On-Chip Supporting Module Access Timing ...................................................... 72 2.9.4 On-Chip HCAN Module Access Timing............................................................. 74 2.9.5 External Address Space Access Timing .............................................................. 76 2.10 Usage Note........................................................................................................................ 76 2.10.1 TAS Instruction ................................................................................................... 76 2.10.2 Caution to Observe when Using Bit Manipulation Instructions .......................... 76 Section 3 MCU Operating Modes .................................................................................. 77 3.1 Overview .......................................................................................................................... 77 3.1.1 Operating Mode Selection ................................................................................... 77 3.1.2 Register Configuration......................................................................................... 78 3.2 Register Descriptions........................................................................................................78 3.2.1 Mode Control Register (MDCR) ......................................................................... 78 3.2.2 System Control Register (SYSCR)...................................................................... 79 3.2.3 Pin Function Control Register (PFCR) ................................................................ 80 3.3 Operating Mode Descriptions ........................................................................................... 82 3.3.1 Mode 4................................................................................................................. 82 3.3.2 Mode 5................................................................................................................. 82 3.3.3 Mode 6................................................................................................................. 82 3.3.4 Mode 7................................................................................................................. 82 3.4 Pin Functions in Each Operating Mode ............................................................................ 83 3.5 Address Map in Each Operating Mode............................................................................. 83 Section 4 Exception Handling ......................................................................................... 87 4.1 Overview .......................................................................................................................... 87 4.1.1 Exception Handling Types and Priority............................................................... 87 4.1.2 Exception Handling Operation ............................................................................ 88 4.1.3 Exception Vector Table ....................................................................................... 88 4.2 Reset ................................................................................................................................. 90 4.2.1 Overview ............................................................................................................. 90 4.2.2 Reset Sequence .................................................................................................... 90 4.2.3 Interrupts after Reset............................................................................................ 92 4.2.4 State of On-Chip Supporting Modules after Reset Release ................................. 93 4.3 Traces................................................................................................................................ 93 4.4 Interrupts........................................................................................................................... 94 4.5 Trap Instruction ................................................................................................................ 95 4.6 Stack Status after Exception Handling.............................................................................. 96 |
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