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HD64338085R Datasheet(PDF) 10 Page - Renesas Technology Corp |
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HD64338085R Datasheet(HTML) 10 Page - Renesas Technology Corp |
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10 / 697 page  Rev. 3.00 Aug 23, 2006 Page x of lxxviii Item Page Revision (See Manual for Details) 2.8.3 Bit-Manipulation Instruction 57 • Prior to executing BSET instruction MOV.B #H'80, R0L 59 • Prior to executing BCLR instruction MOV.B #H'3F, R0L 3.1 Exception Sources and Vector Address Table 3.1 Exception Sources and Vector Address 62 Table amended Source Origin Exception Sources Vector Number Vector Address Priority Address break Break conditions satisfied 5 H'000A to H'000B Internal interrupts* 19 to 43 H'0026 to H'0057 Low 3.2 Reset 63, 64 Replaced 3.3 Interrupts 65 Description amended .. The interrupt controller can set interrupts other than NMI to one of three mask levels in order to control multiple interrupts. The interrupt priority registers A to E (IPRA to IPRE) of the interrupt controller set the interrupt mask level. 3.5.1 Notes on Stack Area Use 68 Description amended To save register values, use PUSH.W Rn (MOV.W Rn, @–SP) or PUSH.L ERn (MOV.L ERn, @–SP). To restore register values, use POP.W Rn (MOV.W @SP+, Rn) or POP.L ERn (MOV.L @SP+, ERn). During interrupt exception handling or when an RTE instruction is executed, CCR contents are saved and restored in word size. Section 4 Interrupt Controller 4.1 Features 73 Description amended • Mask levels settable with IPR An interrupt priority register (IPR) is provided for setting interrupt mask levels. Three mask levels can be set for each module for all interrupts except NMI and address break. |
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