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R5S72060W200FPV Datasheet(PDF) 7 Page - Renesas Technology Corp |
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R5S72060W200FPV Datasheet(HTML) 7 Page - Renesas Technology Corp |
7 / 1188 page Rev. 3.00 Jun. 18, 2008 Page vii of xxiv • Examples The notation used for register names, bit names, numbers, and symbols in this manual is described below. CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter input clock.Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0. 14.3 Operation The style (register name)_(channel number) is used in cases where the same or a similar function is implemented on more than one channel. Example: CMCSR_0 When bit names are given in this manual, the higher-order bits are to the left and the lower-order bits are to the right. Example: CKS1, CKS0 (1) Registers (2) Bits Rev. 0.50, 10/04, page 416 of 914 14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1) 14.3.1 Interval Count Operation (4) (2) (3) (1) Binary numbers are given as B'xxxx, hexadecimal are given as H'xxxx, and decimal are given as xxxx. Examples: B'11 or 11, H'EFA0, 1234 (3) Numbers An overbar is added to the names of active-low signals. Example: WDTOVF Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this manual. (4) Symbols When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time, a f/4 clock is selected. |
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