M65665DSP

Rev.2.00, Sep.04.2003, page 10 of 17

I

When using any or all of the information contained in this table, please be sure to evaluate all information as a total

system before making a final decision on the applicability of the information and products.

1/9 Ref. Value

Address

Bit

Symbol

Read/

Write

Reset

Value

NTSC

Trinorma

Remarks

00h

<7>

DISP

W/R

0

1h

1h

Sub picture display : [0] off , [1] on

<6>

SIZE_V

W/R

0

0

0

Sub picture vertical size : [0] 1/9 , [1] 1/16

<5>

SIZE_H

W/R

0

0

0

Sub picture horizontal size : [0] 1/9 , [1] 1/16

<4>

WEN

W/R

0

1h

1h

Sub picture : [0] Still , [1] Moving

<3>

BGC

W/R

0

0

0

Back ground display : [0] off , [1] on

<2>

BGCS

W/R

0

0

0

Sub picture mute : [0] off , [1] on

<1>

FREE_RUN

W/R

0

0

0

VCXO oscilation : [0] Lock , [1] Free run

<0>

XTALVLATCH

W/R

0

0

1h

X'tal change V-Latch Enable : [0] disable , [1]

enable

01h

<7:0>

VXA<7:0>

W/R

0

20h

20h

Sub picture vertical position

02h

<7:0>

HXA<7:0>

W/R

0

20h

20h

Sub picture horizontal position

03h

<7>

DECODE

W/R

0

0

0

Sub picture color decoder reset : [1] reset

<6:0>

CONTRAST<6:0>

W/R

0

32h

32h

Sub picture Y or R DAC output amplitude

control

04h

<7>

KILLER

W/R

0

0

0

Sub picture color killer : [0] enable , [1] disable

<6:0>

U_DAC<6:0>

W/R

0

32h

32h

Sub picture U or G DAC output amplitude

control

05h

<7>

GRC

W/R

0

1h

1h

Frame display : [0] off , [1] on

<6>

YUVN_RGB_SEL

W/R

0

0

0

PIP output mode selection : [0] YUV , [1] RGB

<5:0>

TINT<5:0>

W/R

0

0

0

Sub picture TINT control

06h

<7:6>

EXT_SC_SEL<1:0>

W/R

0

1h

1h

Sub picture c-sync sep. selection :

[0] int. digital , [1] int. auto slice , [2] ext.(18

pin) , [3] int. analog

<5:4>

DCONT<1:0>

W/R

0

0

0

Sub picture int. c-sync sep. threshhold setting.

<3:0>

HT<3:0>

W/R

0

Ah

Ah

Sub picture display timing adjust

07h

<7:6>

INPUT_SEL<1:0>

W/R

0

2h

2h

Sub picture input selection : [0] YC , [1] N.A. ,

[2] CVBS , [3] YUV

<5:0>

BG_START<5:0>

W/R

0

0Fh

0Fh

Sub picture Burst Gate Pulse position setting

08h

<7:4>

ADJ<3:0>

W/R

0

4h

4h

Main/Sub switch delay control

<3:0>

YDL<3:0>

W/R

0

Ah

Ah

Sub picture Y/C delay adjust

09h

<7:5>

BGBY<2:0>

W/R

0

0

0

Back ground U level setting

<4:0>

Y_OFFSET<4:0>

W/R

0

0Fh

0Fh

Sub picture Y bright control

0Ah

<7>

VCHIP ONLY

W/R

0

1h

1h

V-chip decode mode : [0] off , [1] on

<6:4>

BGRY<2:0>

W/R

0

0

0

Back ground V level setting

<3:0>

BGY<3:0>

W/R

0

6h

6h

Back ground Y level setting

0Bh

<7:4>

PEDESTV<3:0>

W/R

0

0

0

Sub picture V pedestal level (2's comp)

<3:0>

PEDESTU<3:0>

W/R

0

0

0

Sub picture U pedestal level (2's comp)