MITSUBISHI LSIs

M5M5V5A36GP-75,85

18874368-BIT(524288-WORD BY 36-BIT)

Flow-Through NETWORK SRAM

5/19

Preliminary

M5M5V5A36GP REV.0.1

Read Operations

Flow-Through Read

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1#, E2 and

E3#) are active, the write enable input signal (W#) is deasserted high, and ADV is asserted low.

Write Operation

Single Late Write

Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1#, E2 and E3#)

are active, the write enable input signal (W#) is asserted low, and ADV is asserted low.

In Single Late Write the RAM requires Data in one rising clock edge later than the edge used to load Address and Control.

CLK

ADD

E1#

ADV

W#

BWx#

DQ

Q(A)

Q(B)

Read A

Deselect

Read B

Read C

Read D

Read E

A

B

C

D

E

Q(C)

#0

#1

#2

#3

#4

Q(D)

CLK

A

B

C

D

E

ADD

E1#

ADV

W#

BWx#

DQ

Write A

Deselect

Write B

Write C

Write D

Write E

D(A)

D(C)

D(B)

D(D)

#0

#1

#2

#3

#4