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HA16174P Datasheet(PDF) 3 Page - Renesas Technology Corp |
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HA16174P Datasheet(HTML) 3 Page - Renesas Technology Corp |
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3 / 37 page  HA16174P/FP Rev.1.00 Jan 06, 2006 page 3 of 36 Block Diagram Gate Driver +/– 1.0 A (PEAK) 5 V Internal Bias Circuit Ground VCC IAC CS CAO GND FB EO OUT 27.5 V 5 V VREF Generator PFC-ON 0.1 µ VREF UVL PFC-DT RAMP RT K = 0.20 K = 0.05 B+OVP PFC-OFF 25 µA SS CT PG Oscillator 65 kHz 15.4 µs 770 ns 0.65 V 3.6 V VAMP Gain Select B+ GOOD FB LOW PGADJ DELAY VREF GOOD VREF GOOD In Out CLIMIT 3.3 k 55 k CAMP VREF IMO = K × {IAC × (VEO – 1V)} IMO IAC 2.5 V K – 0.30 V 0.50 V VREF GOOD VREF 2.40 V 100 µA 10 µA DELAY RESET 2.50 V VREF 1.25 V 1.75 V 1.60 V PG DELAY PFC DELAY PFC DELAY IN OUT IN OUT PG DELAY DELAY RESET Shut down 4.0 V 2.688 V 2.638 V 2.638 V 3.0 V B+PG RESET B+PG RESET VREF SS Gain Selector 0.95 V Shut down Reset: Vcc<5 V UVLO H L 10.5 V 9.0 V R S Q Q R S Q Q R S Q Q S R Q Q S R Q Q S R Q Q S R Q Q 6 1 3 15 2 11 16 9 10 7 12 8 14 13 5 4 |
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