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HD74HC595FPEL Datasheet(PDF) 1 Page - Renesas Technology Corp |
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HD74HC595FPEL Datasheet(HTML) 1 Page - Renesas Technology Corp |
1 / 11 page Rev.2.00 Mar 30, 2006 page 1 of 10 HD74HC595 8-bit Shift Register/Latch (with 3-state outputs) REJ03D0634-0200 (Previous ADE-205-514) Rev.2.00 Mar 30, 2006 Description This device each contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output pins for cascading. Both the shift register and storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register state will always be one clock pulse ahead of the storage register. Features • High Speed Operation: t pd (RCK to Q) = 17 ns typ (CL = 50 pF) • High Output Current: Fanout of 15 LSTTL Loads (Q A to QH outputs) • Wide Operating Voltage: V CC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: I CC (static) = 4 µA max (Ta = 25°C) • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74HC595P DILP-16 pin PRDP0016AE-B (DP-16FV) P — HD74HC595FPEL SOP-16 pin (JEITA) PRSP0016DH-B (FP-16DAV) FP EL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table Inputs RCK SCK SCLR G Function X X X H QA to QH high impedance X X L X Shift register cleared QH’ = L X H X Shift register clocked Qn = Qn – 1, QA = SER X H X Contents of shift register transferred to output latches |
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