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4583 Datasheet(PDF) 74 Page - Renesas Technology Corp |
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4583 Datasheet(HTML) 74 Page - Renesas Technology Corp |
74 / 153 page Rev.3.00 Aug 06, 2004 page 74 of 151 REJ03B0009-0300Z 4583 Group PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Note: “R” represents read enabled, and “W” represents write enabled. Not used A/D converter operation clock selection bit A/D converter operation clock division ratio selection bits A/D control register Q3 Q33 Q32 Q31 Q30 at reset : 00002 at RAM back-up : state retained 0 1 0 1 Q31 0 0 1 1 Q30 0 1 0 1 Division ratio Frequency divided by 6 Frequency divided by 12 Frequency divided by 24 Frequency divided by 48 This bit has no function, but read/write is enabled. Instruction clock (INSTCK) On-chip oscillator (f(RING)) R/W TAQ3/TQ3A A/D operation mode selection bit Not used Not used Analog input pin selection bits A/D control register Q1 at RAM back-up : state retained at reset : 00002 Q13 Q12 Q11 Q10 A/D conversion mode Comparator mode This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. AIN0 AIN1 R/W TAQ1/TQ1A This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. P61 AIN1 P60 AIN0 Not used Not used P61/AIN1 pin function selection bit P60/AIN0 pin function selection bit 0 1 0 1 0 1 0 1 Q23 Q22 Q21 Q20 R/W TAQ2/TQ2A A/D control register Q2 at RAM back-up : state retained at reset : 00002 0 1 0 1 0 1 0 1 |
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