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4508 Datasheet(PDF) 24 Page - Renesas Technology Corp |
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4508 Datasheet(HTML) 24 Page - Renesas Technology Corp |
24 / 142 page Rev.1.02 2006.12.22 page 24 of 140 REJ03B0148-0102 4508 Group (2) External interrupt control registers • Interrupt control register I1 Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the TI1A in- struction. The TAI1 instruction can be used to transfer the contents of register I1 to register A. Table 8 External interrupt control register Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. I13 I12 I11 I10 INT pin input control bit (Note 2) Interrupt valid waveform for INT pin/ return level selection bit (Note 2) INT pin edge detection circuit control bit INT pin timer 1 control enable bit Interrupt control register I1 R/W TAI1/TI1A at RAM back-up : state retained at reset : 00002 INT pin input disabled INT pin input enabled Falling waveform (“L” level of INT pin is recognized with the SNZI0 instruction)/“L” level Rising waveform (“H” level of INT pin is recognized with the SNZI0 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled 0 1 0 1 0 1 0 1 |
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