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4508 Datasheet(PDF) 58 Page - Renesas Technology Corp |
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4508 Datasheet(HTML) 58 Page - Renesas Technology Corp |
58 / 142 page Rev.1.02 2006.12.22 page 58 of 140 REJ03B0148-0102 4508 Group (5) External clock When the external signal clock is used for the main clock (f(XIN)), connect the XIN pin to the clock source and leave XOUT pin open (Figure 54). Do not execute the CRCK instruction in program. Be careful that the maximum value of the oscillation frequency when using the external clock differs from the value when using the ce- ramic resonator (refer to the recommended operating condition). Also, note that the RAM back-up mode (POF instruction) cannot be used when using the external clock. (6) Clock control register MR Register MR controls the selection of operation mode and the opera- tion source clock, and enable/stop of main clock. Set the contents of this register through register A with the TMRA instruction. In addition, the TAMR instruction can be used to transfer the contents of register MR to register A. (7) Clock control register RG Register RG controls the on-chip oscillator. Set the contents of this register through register A with the TRGA instruction. Table 23 Clock control register MR Fig. 54 External clock input circuit 4508 XIN XOUT External oscillation circuit VDD VSS Do not execute the CRCK instruction in program. * Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: Main clock cannot be stopped when the main clock is selected for the operation source clock. 3: The stopped clock cannot be selected for the operation source clock. In order to switch the operation source clock, generate the oscillation stabiliz- ing wait time by software first and set the oscillation of the destination clock to be enabled. 4: On-chip oscillator cannot be stopped when the on-chip oscillator is selected for the operation source clock. 5: When changing the setting of MR1 and MR0 from “00” to “11”, make settings in the sequence “00” → “01” → “11”. When changing the setting of MR1 and MR0 from “11” to “0”, make settings in the sequence “11” → “01” → “00”. MR3 Clock control register MR Operation mode Through mode (frequency not divided) Frequency divided by 2 mode Frequency divided by 4 mode Frequency divided by 8 mode Main clock (f(XIN)) oscillation enabled Main clock (f(XIN)) oscillation stop Main clock (f(XIN)) On-chip oscillator clock (f(RING)) at reset : 11012 at RAM back-up : 11012 MR3 0 0 1 1 R/W TAMR/TMRA Main clock f(XIN) control bit (Notes 2, 5) Operation source clock selection bit (Notes 3, 5) Operation mode selection bits 0 1 0 1 MR2 0 1 0 1 MR1 MR0 MR2 0 1 On-chip oscillator (f(RING)) oscillation enabled On-chip oscillator (f(RING)) oscillation stop On-chip oscillator (f(RING)) control bit (Note 4) Clock control register RG W TRGA at RAM back-up : 02 at reset : 02 RG0 |
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