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4508 Datasheet(PDF) 48 Page - Renesas Technology Corp |
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4508 Datasheet(HTML) 48 Page - Renesas Technology Corp |
48 / 142 page Rev.1.02 2006.12.22 page 48 of 140 REJ03B0148-0102 4508 Group Fig. 42 Power-on reset operation Name D0, D1 D2/AIN4, D3/AIN5 P00/SIN, P01/SOUT, P02/SCK P03 P10 P11/CNTR1 P12/CNTR0 P13/INT P20/AIN0, P21/AIN1 Notes 1: Output latch is set to “1.” 2: The output structure is N-channel open-drain. 3: Pull-up transistor is turned OFF. Function D0, D1 D2, D3 P00, P01, P02 P03 P10 P11 P12 P13 P20, P21 State High-impedance (Notes 1, 2) High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) (2) Power-on reset (only for H version) Reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. When the built-in power-on re- set circuit is used, set the time for the supply voltage to rise from 0 V to the minimum voltage of recommended operating conditions to 100 µs or less. If the rising time exceeds 100 µs, connect a capacitor between the RESET pin and Vss at the shortest distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage. (3) System reset instruction (SRST) By executing the SRST instruction, “L” level is output to RESET pin and system reset is performed. Table 17 Port state at reset VDD Power-on Reset released Internal reset signal Reset state Power-on reset circuit output →← 100 µs or less Reset state Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. |
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