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4508 Datasheet(PDF) 39 Page - Renesas Technology Corp |
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4508 Datasheet(HTML) 39 Page - Renesas Technology Corp |
39 / 142 page 4508 Group Rev.1.02 2006.12.22 page 39 of 140 REJ03B0148-0102 Note: “R” represents read enabled, and “W” represents write enabled. (1) A/D control register Q1 Register Q1 is used to select the operation mode and one of analog input pins. Set the contents of this register through register A with the TQ1A instruction. The TAQ1 instruction can be used to transfer the contents of register Q1 to register A. (2) Operating at A/D conversion mode The A/D conversion mode is set by setting the bit 3 of register Q1 to “0.” (3) Successive comparison register AD Register AD stores the A/D conversion result of an analog input in 10-bit digital data format. The contents of the high-order 8 bits of this register can be stored in register B and register A with the TABAD in- struction. The contents of the low-order 2 bits of this register can be stored into the high-order 2 bits of register A with the TALA instruc- tion. However, do not execute these instructions during A/D conversion. When the contents of register AD is n, the logic value of the compari- son voltage Vref generated from the built-in DA converter can be obtained with the reference voltage VDD by the following formula: Logic value of comparison voltage Vref Vref = ✕ n n: The value of register AD (n = 0 to 1023) VDD 1024 Table 12 A/D control registers (4) A/D conversion completion flag (ADF) A/D conversion completion flag (ADF) is set to “1” when A/D conver- sion completes. The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction. The ADF flag is cleared to “0” when the interrupt occurs or when the next instruction is skipped with the skip instruction. (5) A/D conversion start instruction (ADST) A/D conversion starts when the ADST instruction is executed. The conversion result is automatically stored in the register AD. (6) Operation description A/D conversion is started with the A/D conversion start instruction (ADST). The internal operation during A/D conversion is as follows: ➀ When the A/D conversion starts, the register AD is cleared to “00016.” ➁ Next, the topmost bit of the register AD is set to “1,” and the com- parison voltage Vref is compared with the analog input voltage VIN. ➂ When the comparison result is Vref < VIN, the topmost bit of the register AD remains set to “1.” When the comparison result is Vref > VIN, it is cleared to “0.” The 4508 Group repeats this operation to the lowermost bit of the register AD to convert an analog value to a digital value. A/D conver- sion stops after 62 machine cycles (31 µs when f(XIN) = 6.0 MHz in high-speed mode) from the start, and the conversion result is stored in the register AD. An A/D interrupt activated condition is satisfied and the ADF flag is set to “1” as soon as A/D conversion completes (Figure 32). Q13 A/D control register Q1 A/D operation mode selection bit at reset : 00002 at RAM back-up : state retained 0 1 Q12 0 0 0 0 1 1 1 1 A/D conversion mode Comparator mode Selected pins AIN0 AIN1 Not available Not available AIN4 AIN5 Not available Not available Q11 0 0 1 1 0 0 1 1 Q11 Q10 0 1 0 1 0 1 0 1 Q12 Q10 Analog input pin selection bits R/W TAQ1/TQ1A |
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