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M37481MXT-XXXSP Datasheet(PDF) 11 Page - Renesas Technology Corp |
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M37481MXT-XXXSP Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 98 page  MITSUBISHI MICROCOMPUTERS 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 10 PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. CPU Mode Register The stack page selection bit is assigned to the CPU mode regis- ter. This register is allocated at address 00FB16. Fig. 7 Structure of CPU mode register FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The 7480/7481 group uses the standard 740 family CPU. Refer to the table of 740 family addressing modes and machine instruc- tions or the MELPS 740 programming manual for details on the instruction set. Machine-resident 740 family instructions are as follows: 1. The FST and SLW instructions are not available. 2. The MUL and DIV instructions are available. 3. The WIT instruction is available. (Note) 4. The STP instruction is available. (Note) Note: When using these instructions, refer to the corresponding chapter “STP and WIT instruction control” below. CPU mode register (CPUM: address 00FB16) b7 b0 Stack page selection bit (Note) 0 : Page 0 1 : Page 1 System clock division proportion selection bit 0 : f = f(XIN)/2 (high-speed mode) 1 : f = f(XIN)/8 (medium-speed mode) Not used. These bits must always be set to “0”. Watchdog timer L count source selection bit 0 : f(XIN)/8 1 : f(XIN)/16 Note : In the models of RAM size under 192 bytes, set this bit to “0”. Not used (undefined at read) Not used (undefined at read) |
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