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HD404849H Datasheet(PDF) 9 Page - Renesas Technology Corp

Part # HD404849H
Description  4-Bit Single-Chip Microcomputer
Download  127 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD404849H Datasheet(HTML) 9 Page - Renesas Technology Corp

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HD404849 Series
7
Memory Map
ROM Memory Map
The ROM memory map is shown in figure 1 and described below.
Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses
of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the
vector address.
Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a
subroutine in this area in response to the CAL instruction.
Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction.
Program Area ($0000–$1FFF: HD404848; $0000–$2FFF: HD4048412; $0000–$3FFF: HD404849,
HD4074849): Used for program coding.
0
15
63
4095
8191
12287
16383
$0000
$000F
$003F
$0FFF
$1FFF
$2FFF
$3FFF
HD404849/
HD4074849
program area
(16,384 words)
HD4048412
program area
(12,288 words)
HD404848
program area
(8,192 words)
Pattern area
(4,096 words)
Zero-page
subroutine area
(64 words)
Vector address area
(16 words)
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
JMPL instruction
(jump to
RESET, STOPC routine)
JMPL instruction
(jump to
INT routine)
JMPL instruction
(jump to
INT routine)
JMPL instruction
(jump to timer A routine)
JMPL instruction
(jump to timer B, INT routine)
JMPL instruction
(jump to timer C, INT routine)
3
JMPL instruction
(jump to timer D routine)
JMPL instruction
(jump to A/D, serial routine)
2
0
1
Figure 1 ROM Memory Map


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