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HD407A4639RF Datasheet(PDF) 9 Page - Renesas Technology Corp

Part # HD407A4639RF
Description  4-Bit Single-Chip Microcomputer
Download  135 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD407A4639RF Datasheet(HTML) 9 Page - Renesas Technology Corp

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HD404639R Series
7
RAM Memory Map
The MCU contains a 1,152-digit
× 4-bit RAM area consisting of a memory register area, a data area, and a
stack area. In addition, an interrupt control bits area, special register area, and register flag area are mapped
onto the same RAM memory space as a RAM-mapped register area outside the above areas. The RAM
memory map is shown in figure 2 and described as follows.
RAM-Mapped Register Area ($000–$03F):
• Interrupt Control Bits Area ($000–$003)
This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit
manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the
instructions can be used for each bit. Limitations on using the instructions are shown in figure 4.
• Special Function Register Area ($004–$01E, $024–$03F)
This area is used as mode registers and data registers for external interrupts, serial interface 1, serial
interface 2, timer/counters, voltage comparator, and as data control registers for I/O ports. The
structure is shown in figures 2 and 5. These registers can be classified into three types: write-only (W),
read-only (R), and read/write (R/W). RAM bit manipulation instructions cannot be used for these
registers.
• Register Flag Area ($020–$023)
This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3).
These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and
TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using
the instructions are shown in figure 4.
Memory Register (MR) Area ($040–$04F): Consisting of 16 addresses, this area (MR0–MR15) can be
accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6.
Data Area ($090–$2EF): Consists of 464 digits from $090 to $25F in two banks, which can be selected
by setting the bank register (V: $03F). Before accessing this area, set the bank register to the required
value (figure 7). The area from $260 to $2EF is accessed without setting the bank register.
Stack Area ($3C0–$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and
carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a
16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save
conditions are shown in figure 6.
The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can
only be restored by the RTNI instruction. Any unused space in this area is used for data storage.


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