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HD4074329S Datasheet(PDF) 11 Page - Renesas Technology Corp |
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HD4074329S Datasheet(HTML) 11 Page - Renesas Technology Corp |
11 / 103 page HD404054 Series/HD404094 Series 9 0 1 2 3 Bit 3 Bit 2 Bit 1 Bit 0 IMTA (IM of timer A) IFTA (IF of timer A) IM1 (IM of INT1) IF1 (IF of INT1) IMTC (IM of timer C) IFTC (IF of timer C) IMS1 (IM of serial interface 1) IFS1 (IF of serial interface 1) IMTD (IM of timer D) IFTD (IF of timer D) $000 $001 $002 $003 Interrupt control bits area IM0 (IM of INT0) IF0 (IF of INT0) RSP (Reset SP bit) IE (Interrupt enable flag) 32 33 ICSF (Input capture status flag) $020 $021 Register flag area WDON (Watchdog on flag) ICEF (Input capture error flag) RAME (RAM enable flag) Not used IF: IM: IE: SP: Interrupt request flag Interrupt mask Interrupt enable flag Stack pointer Bit 3 Bit 2 Bit 1 Bit 0 Not used Not used Not used Not used Not used Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas IE IM IF ICSF ICEF RAME RSP WDON Not used SEM/SEMD REM/REMD TM/TMD Allowed Allowed Allowed Not executed Allowed Allowed Not executed Allowed Inhibited Allowed Not executed Inhibited Not executed Not executed Inhibited Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. If the TM or TDM instruction is executed for the inhibited bits or non-existing bits, the value in ST becomes invalid. Figure 4 Usage Limitations of RAM Bit Manipulation Instructions |
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