RD30LDT595

REJ03D0906-0200 Rev.2.00, Jun 16, 2008

Page 2 of 7

Logic Diagram

D

Q

CK

CLK

S-in

Latch

Enable

D

Q

L

D

Q

CK

D

Q

L

Output wrong action

protection circuit

Q8

Q1

S-out

Function Table

Inputs

Outputs

S-in

CLK

*1

Latch

Enable

Q1 to Q8

S-out

L

IN

L

L

t - 1

L

L

IN

H

L

Z

L

H

IN

L

L

t - 1

H

H

IN

H

L

L

H

H

IN

H

H

Z

H

IN : Input the following signal in CLK

12

7

8

*1

H : High level

L : Low level

Z : High impedance

t - 1 : Output level before the indicated steady state input conditions were established.