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M62421SP Datasheet(PDF) 9 Page - Renesas Technology Corp |
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M62421SP Datasheet(HTML) 9 Page - Renesas Technology Corp |
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9 / 14 page  M62421SP/FP REJ03F0208-0201 Rev.2.01 Mar 31, 2008 Page 9 of 13 Data and Clock CLK DAT D0 D1 D2 D3 D10 D11 D12 DATA is read by CLK rise edge. Latch signal is read by CLK fall edge. Latch signal "H" Bus Line Timing Specification 75% 25% tr tf tWHC tWLC tcr tSD tHD Item Symbol Min Max Units CLK clock frequency tcr 4 — µs The HIGH period of the clock tWHC 1.6 — µs The LOW period of the clock tWLC 1.6 — µs Rise time of CLK line tr — 0.4 µs Fall time of CLK line tf — 0.4 µs Set-up time DATA tSD 0.8 — µs Hold time DATA tHD 0.8 — µs |
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