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R1EX24008ATA00A Datasheet(PDF) 8 Page - Renesas Technology Corp |
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R1EX24008ATA00A Datasheet(HTML) 8 Page - Renesas Technology Corp |
8 / 22 page R1EX24008Axx00A Device Address (A0, A1, A2) Two devices can be wired for one common data bus line as maximum. Device address pins are used to distinguish each device and device address pins should be connected to V CC or VSS. When device address code provided from SDA pin matches corresponding hard-wired device address pins A0 to A2, that one device can be activated. Pin Connections for A0 to A2 Pin connection Memory size Max connect number A2 A1 A0 Note 8k bit 2 V CC/VSS ×*2 ×*2 Use A0,A1 for memory address a8and a9 Note: 1. During floating, “V CC/VSS” are fixed to VSS. 2. Floating state can be possible. Write Protect (WP) When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in the following table. When the WP is low, write operation for all memory arrays are allowed. The read operation is always activated irrespective of the WP pin status. Write Protect Area Write protect area WP pin status 8k bit V IH Upper 1/2 (4k bit) V IL Normal read/write operation REJ03C0351-0001 Rev.0.01 Dec. 28, 2007 Page 8 of 20 |
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