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R1Q5A3618RBG-50RS0 Datasheet(PDF) 5 Page - Renesas Technology Corp |
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R1Q5A3618RBG-50RS0 Datasheet(HTML) 5 Page - Renesas Technology Corp |
5 / 26 page R1Q2A3636B/R1Q2A3618B/R1Q2A3609B REJ03C0341-0003 Rev.0.03 Apr. 11, 2008 Page 5 of 24 Pin Description Name I/O type Descriptions Notes SA Input Synchronous address inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K for READ cycles and must meet the setup and hold times around the rising edge of /K for WRITE cycles. All transactions operate on a burst-of-two words (one clock period of bus activity). These inputs are ignored when device is deselected. /R Input Synchronous read: When low, this input causes the address inputs to be registered and a READ cycle to be initiated. This input must meet setup and hold times around the rising edge of K. /W Input Synchronous write: When low, this input causes the address inputs to be registered and a WRITE cycle to be initiated. This input must meet setup and hold times around the rising edge of K. /BWx Input Synchronous byte writes: When low, these inputs cause their respective byte to be registered and written during WRITE cycles. These signals must meet setup and hold times around the rising edges of K and /K for each of the two rising edges comprising the WRITE cycle. See Byte Write Truth Table for signal to data relationship. K, /K Input Input clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data on the rising edge of K and the rising edge of /K. /K is ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges. These balls cannot remain VREF level. C, /C Input Output clock: This clock pair provides a user-controlled means of tuning device output data. The rising edge of /C is used as the output timing reference for first output data. The rising edge of C is used as the output timing reference for second output data. Ideally, /C is 180 degrees out of phase with C. C and /C may be tied high to force the use of K and /K as the output reference clocks instead of having to provide C and /C clocks. If tied high, C and /C must remain high and not to be toggled during device operation. These balls cannot remain VREF level. /DOFF Input DLL disable: When low, this input causes the DLL to be bypassed for /DOFF Input stable, low frequency operation. ZQ Input Output impedance matching input: This input is used to tune the device outputs to the system data bus impedance. Q and CQ output impedance are set to 0.2 × RQ, where RQ is a resistor from this ball to ground. This ball can be connected directly to VDDQ, which enables the minimum impedance mode. This ball cannot be connected directly to VSS or left unconnected. TMS TDI Input IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not TMS Input connected if the JTAG function is not used in the circuit. TCK Input IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to VSS if the JTAG function is not used TCK Input in the circuit. D0 to Dn Input Synchronous data inputs: Input data must meet setup and hold times around the rising edges of K and /K during WRITE operations. See Pin Arrangement figures for ball site location of individual signals. The ×9 device uses D0 to D8. Remaining signals are not used. The ×18 device uses D0 to D17. Remaining signals are not used. The ×36 device uses D0 to D35. CQ, /CQ Output Synchronous echo clock outputs: The edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q tristates. TDO Output IEEE 1149.1 test output: 1.8 V I/O level. Q0 to Qn Output Synchronous data outputs: Output data is synchronized to the respective C and /C, or to the respective K and /K if C and /C are tied high. This bus operates in response to /R commands. See Pin Arrangement figures for ball site location of individual signals. The ×9 device uses Q0 to Q8. Remaining signals are not used. The ×18 device uses Q0 to Q17. Remaining signals are not used. The ×36 device uses Q0 to Q35. |
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