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M66311FP Datasheet(PDF) 3 Page - Renesas Technology Corp |
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M66311FP Datasheet(HTML) 3 Page - Renesas Technology Corp |
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3 / 10 page  M66311P/FP REJ03F0177-0201 Rev.2.01 Mar 31, 2008 Page 3 of 9 Functional Description As M66311P/FP uses silicon gate CMOS process, it realizes high-speed and high-output currents sufficient for LED drive while maintaining low power consumption and allowance for high noises. Each bit of a shiftregister consists of two flip–flops having independent clocks for shifting and latching. As for clock input, shift clock input CKS and latch clock input CKL are independent from each other, shift and latch operations being made when “L” changes to “H”. Serial data input A is the data input of the first–step shiftregister and the signal of A shifts shifting registers one by one when a pulse is impressed to CKS. When A is “H”, the signal of “L” shifts. When the pulse is impressed to CKL, the contents of the shifting register at that time are stored in a latching register, and they appear in the outputs from Q A to QP. Outputs from Q A to QP are open drain outputs. To extend the number of bits, use the serial data output SQP which shows the output of the shifting register of the 16th bit. If CKS and CKL are connected, the state of the shifting register with one clock delay is outputted to QA to QP. When reset input R is changed to “L”, Q A to QP and SQP are reset. In this case, shifting and latching registers are set. If “H” is impressed to output enable input OE, Q A to QP reaches the high impedance state, but SQP does not reach the high impedance state. Furthermore, change in OE does not affect shift operation. Function Table (Note) Operation Mode Reset Shift latch operation Output disable Input Parallel Data Output R L H H H H X CK S X ↑ X ↑ X X CK L X X ↑ X ↑ X A X H X L X X OE X L L L L H QA Z QA0 L QA0 Z Z QB Z QB0 q A 0 QB0 q A 0 Z QC Z QC0 q B 0 QC0 q B 0 Z QD Z QD0 q C 0 QD0 q C 0 Z QE Z QE0 q D 0 QE0 q D 0 Z QF Z QF0 q E 0 QF0 q E 0 Z QG Z QG0 q F 0 QG0 q F 0 Z QH Z QH0 q G 0 QH0 q G 0 Z QI Z QI0 q H 0 QI0 q H 0 Z QJ Z QJ0 q I 0 QJ0 q I 0 Z QK Z QK0 q J 0 QK0 q J 0 Z QL Z QL0 q K 0 QL0 q K 0 Z QM Z QM0 q L 0 QM0 q L 0 Z QN Z QN0 q M 0 QN0 q M 0 Z QO Z QO0 q N 0 QO0 q N 0 Z QP Z QP0 q O 0 QP0 q O 0 Z Shift t1 Latch t2 Shift t1 Latch t2 Output lighting "H" Remarks Serial Data Output SQ P L q O 0 q O 0 q O 0 q O 0 q P – – Output lights-out "L" Note ↑: Change from low-level to high-level Q0: Output state Q before CK L changed X: Irrelevant q 0: Contents of shift register before CK S changed q: Contents of shift register t1, t2: t2 is set after t1 is set Z: High impedance |
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