RD151TS3315ARP, RD151TS3325ARP

Rev.1.00 May 11, 2006 page 4 of 8

AC Electrical Characteristics / SSC Clock Output

Item

Symbol

Min

Typ

Max

Unit

Test Conditions

Notes

Operating current

—

24

30

mA

XIN = 40 MHz

Cycle to cycle jitter *

1

—

|100|

—

ps

SSC =

±1.5% (TS3315ARP)

SSC = –3.0% (TS3325ARP)

Figure 1

Slew rate

—

2.0

5.0

V/ns

0.2

Clock duty cycle

45

50

55

%

Stabilization time

*2

—

—

2

ms

Notes: Parameters are target of design. Not 100% tested in production.

1. Cycle to cycle jitter is included spread spectrum modulation.

2. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input signal after

power up.

SSCOUT

tcycle n

tcycle n+1

Figure 1 Cycle to cycle jitter