Rev.1.00 Jun. 22, 2004 page 1 of 8

RD74LVC74B

Dual D-type Flip Flops with Preset and Clear

REJ03D0324–0100Z

Rev.1.00

Jun. 22, 2004

Description

The RD74LVC74B has independent data, preset, clear, and clock inputs Q and

Q outputs in a 14 pin package. The

logic level present at the data input is transferred to the output during the positive going transition of the clock pulse.

Preset and clear are independent of the clock and accomplished by a low level at the appropriate input. Low voltage

and high-speed operation is suitable at the battery drive product (note type personal computer) and low power

consumption extends the life of a battery for long time operation.

Features

• V

• All inputs V

• Typical V

• Typical V

• High output current

• Ordering Information

Part Name

Package Type

Package Code

Package

Abbreviation

Taping Abbreviation

(Quantity)

RD74LVC74BFPEL

SOP–14 pin (JEITA)

FP–14DAV

FP

EL (2,000 pcs / reel)

RD74LVC74BTELL

TSSOP–14 pin

TTP–14DV

T

ELL (2,000 pcs / reel)

Function Table

Inputs

Outputs

PR

CLR

CK

D

Q

Q

LH

X

X

H

L

HL

X

X

L

H

LLX

X

H

*1

H

*1

HH

↑

HH

L

HH

↑

LL

H

HHL

X

Q

0

HHHX

Q

0

HH

↓

Q

0

H :

High level

L :

Low level

X :

Immaterial

↓ :

High to Low transition

↑ :

Low to high transition

Level to Q before the indicated steady input conditions were established.

Note:

1. Q and

Q will remain high as long as preset and clear are low, but Q and Q are unpredictable, if preset and

clear go high simultaneously.