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PSD4235G3V-12UI Datasheet(PDF) 8 Page - STMicroelectronics |
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PSD4235G3V-12UI Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 89 page PSD4235G2 8/89 PSD ARCHITECTURAL OVERVIEW PSD devices contain several major functional blocks. Figure 4 shows the architecture of the PSD device family. The functions of each block are de- scribed briefly in the following sections. Many of the blocks perform multiple functions and are user configurable. Memory Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed discus- sion can be found in the section entitled “Memory Blocks“ on page 20. The 4 Mbit primary Flash memory is the main memory of the PSD. It is divided into 8 equally- sized sectors that are individually selectable. The 256 Kbit secondary Flash memory is divided into 4 equally-sized sectors. Each sector is individ- ually selectable. The 64 Kbit SRAM is intended for use as a scratch-pad memory or as an extension to the MCU SRAM. If an external battery is connected to the PSD’s Voltage Stand-by (VSTBY, PE6) signal, data is retained in the event of power failure. Each memory block can be located in a different address space as defined by the user. The access times for all memory types includes the address latching and DPLD decoding time. PLDs The device contains two PLD blocks, the Decode PLD (DPLD) and the Complex PLD (CPLD), as shown in Table 2, each optimized for a different function. The functional partitioning of the PLDs reduces power consumption, optimizes cost/per- formance, and eases design entry. The DPLD is used to decode addresses and to generate Sector Select signals for the PSD inter- nal memory and registers. The DPLD has combi- natorial outputs, while the CPLD can implement more general user-defined logic functions. The CPLD has 16 Output Macrocells (OMC) and 8 combinatorial outputs. The PSD also has 24 Input Macrocells (IMC) that can be configured as inputs to the PLDs. The PLDs receive their inputs from the PLD Input Bus and are differentiated by their output destinations, number of product terms, and Macrocells. The PLDs consume minimal power. The speed and power consumption of the PLD is controlled by the Turbo bit in PMMR0 and other bits in PMMR2. These registers are set by the MCU at run-time. There is a slight penalty to PLD propaga- tion time when not in the Turbo mode. I/O Ports The PSD has 52 I/O pins divided among seven ports (Port A, B, C, D, E, F and G). Each I/O pin can be individually configured for different func- tions. Ports can be configured as standard MCU I/ O ports, PLD I/O, or latched address outputs for MCUs using multiplexed address/data buses The JTAG pins can be enabled on Port E for In- System Programming (ISP). Table 2. PLD I/O MCU Bus Interface The PSD easily interfaces easily with most 16-bit MCUs, either with multiplexed or non-multiplexed address/data buses. The device is configured to respond to the MCU’s control pins, which are also used as inputs to the PLDs. ISP via JTAG Port In-System Programming (ISP) can be performed through the JTAG signals on Port E. This serial in- terface allows complete programming of the entire PSD device. A blank device can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can be multiplexed with other functions on Port E. Table 3 indicates the JTAG pin assignments. In-System Programming (ISP) Using the JTAG signals on Port E, the entire PSD device (memory, logic, configuration) can be pro- grammed or erased without the use of the MCU. Table 3. JTAG SIgnals on Port E In-Application Programming (IAP) The primary Flash memory can also be pro- grammed, or re-programmed, in-system by the MCU executing the programming algorithms out of the secondary Flash memory, or SRAM. The sec- ondary Flash memory can be programmed the same way by executing out of the primary Flash memory. Table 4 indicates which programming methods can program different functional blocks of the PSD. Name Inputs Outputs Product Terms Decode PLD (DPLD) 82 17 43 Complex PLD (CPLD) 82 24 150 Port E Pins JTAG Signal PE0 TMS PE1 TCK PE2 TDI PE3 TDO PE4 TSTAT PE5 TERR |
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