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R8A66597FP Datasheet(PDF) 10 Page - Renesas Technology Corp |
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R8A66597FP Datasheet(HTML) 10 Page - Renesas Technology Corp |
10 / 185 page R8A66597FP/DFP/BG Rev 1.01 Oc t 17, 2008 Page 10 of 183 Confidential 1.6 Functional Overview 1.6.1 Selection of controller functions The controller can toggle between Host functions and Peripheral functions according to what is written to the register. The hardware can automatically identify the USB transmission speed, irrespective of whether the Host or Peripheral function is selected. 1.6.2 Bus interface The controller is compatible with the bus interfaces given below. 1.6.2.1 External bus interface The CPU accesses the control register of the controller using the CPU bus interface. There are two types of access below for the bus interface from the CPU. Access using a chip select pin (CS_N) and three strobe pins (RD_N, WR0_N and WR1_N). 16-bit separate bus Seven address buses (A7-1) and sixteen data buses (D15-0) are used. 16-bit multiplex bus The ALE pin (ALE) and sixteen data buses (D15-0) are used. The data bus uses the address and data in the time division. Separate bus or multiplex bus are selected at the MPBUS pin signal level while canceling the hardware reset. 1.6.2.2 FIFO buffer memory access method This controller is compatible with the following two access types as an access method of the FIFO buffer memory for USB data transmission. Read (write) of the data from the FIFO buffer memory is possible by accessing (read/write) the FIFO port from the CPU (DMAC). (1) CPU access Write the data in, or read the data from, the FIFO buffer memory using the address signal and control signal. (2) DMA access Write the data in the FIFO buffer memory from the CPU’s built-in DMAC or dedicated DMAC, or read the data from the FIFO buffer memory. USB communication is executed by a little endian. A byte endian swap function is provided in the FIFO port access. For 16-bit access, the endian can be changed according to what is written to the register. 1.6.2.3 FIFO buffer memory access method from DMAC To access the FIFO buffer memory through the DMA access, select an access method from the following: (1) Method of using common bus with CPU (2) Method in which dedicated bus (split bus) is used 1.6.3 USB event The controller notifies the events regarding USB operations to the user system through the interrupt. It also notifies that the DMA interface can access the buffer memory of the selected pipe by asserting the DREQ signal. Depending on what the software writes, interrupt notification activation can be selected for the type and factor. |
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