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R1Q5A3618BBG-60R Datasheet(PDF) 8 Page - Renesas Technology Corp

Part # R1Q5A3618BBG-60R
Description  36-Mbit DDRII SRAM 4-word Burst
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R1Q5A3618BBG-60R Datasheet(HTML) 8 Page - Renesas Technology Corp

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R1Q5A3636B/R1Q5A3618B
REJ03C0344-0003 Rev.0.03 Apr.11, 2008
page 8 of 23
K Truth Table
Operation
K
/R
/W
D or Q
Data in
Input
data
D(A1)
D(A2)
D(A3)
D(A4)
Write Cycle:
Load address, input write data
on consecutive K and /K rising
edges
L
L
Output
clock
K(t+1)
/K(t+1)
K(t+2)
/K(t+2)
Data out
Output
data
Q(A1)
Q(A2)
Q(A3)
Q(A4)
Read Cycle:
Load address, output read
data on consecutive C and /C
rising edges
L
H
Output
clock
/C(t+1)
C(t+2)
/C(t+2)
C(t+3)
NOP (No operation)
H
×
High-Z
Standby (Clock stopped)
Stopped
×
×
Previous state
Notes: 1. H: high level, L: low level, ×: don’t care, ↑: rising edge.
2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges,
except if C and /C are high, then data outputs are delivered at K and /K rising edges.
3. /LD and R-/W must meet setup/hold times around the rising edges (low to high) of K and are registered at the
rising edge of K.
4. This device contains circuitry that will ensure the outputs will be in high-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. When clocks are stopped, the following cases are recommended; the case of K = low, /K = high, C = low and
/C = high, or the case of K = high, /K = low, C = high and /C = low. This condition is not essential, but permits
most rapid restart by overcoming transmission line charging symmetrically.
7. A1 refers to the address input during a WRITE or READ cycle. A2, A3 and A4 refer to the 1st, 2nd and 3rd
internal burst address, respectively, in accordance with the linear burst sequence.
Byte Write Truth Table (x36)
Operation
K
/K
/BW0
/BW1
/BW2
/BW3
Write D0 to D35
L
L
L
L
L
L
L
L
Write D0 to D8
L
H
H
H
L
H
H
H
Write D9 to D17
H
L
H
H
H
L
H
H
Write D18 to D26
H
H
L
H
H
H
L
H
Write D27 to D35
H
H
H
L
H
H
H
L
Write nothing
H
H
H
H
H
H
H
H
Notes: 1. H: high level, L: low level,
↑: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation
provided that the setup and hold requirements are satisfied.


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