M30245F8-XXXGP datasheet(8/266 Pages) RENESAS

Part #	M30245F8-XXXGP

Description	SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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8 / 266 page

Rev.2.00

Oct 16, 2006

page 8 of 264

M30245 Group

Description

REJ03B0005-0200

Table 1.3

Pin description

With a 16-bit external data bus, data is written to even addresses when the

WRL signal is "L", and to the odd addresses when the WRH signal is "L". Data

is read when RD is "L".

Port

Function

Pin Name

I/O

Description

Power supply input

Vcc

3.0 to 3.6V

Vss

0V

CPU mode switch

CNVss

I

Connect to Vss: single-chip or memory expansion mode

Connect to Vcc: Microprocessor mode only

External data bus width select

input

BYTE

I

Selects external memory data bus width.

Connect to Vss: 16-bit.

Connect to Vcc: 8-bit.

Reset input

RESET

I

"L" resets the microcomputer.

Clock input

XIN

I

These pins support the main clock generating circuit. Connect a crystal between

the XIN and XOUT pins. To use an external clock, input it to the XIN pin and leave

the XOUT pin open.

Clock output

XOUT

O

Analog power supply input

AVcc

Connect to Vcc.

AVss

Connect to Vss.

Reference voltage input

VREF

I

This is a reference voltage for A/D converter.

Low pass filter

LPF

O

Loop filter for the frequency synthesizer circuit.

USB power supply input

UVcc

Power pin for USB

Vbus detect

VbusDTCT

I

Detects USB host power

USB D+

I/O

USB D+ voltage line interface

USB D-

I/O

USB D- voltage line interface

P0

I/O port

P00 to P07

I/O

This is an 8-bit CMOS I/O port. The input/output port direction register allows

each pin to be set individually. When used for input, the port can be set to

include internal pull-up resistors in 4-pin blocks.

Data bus

D0 to D7

I/O

These pins input and output 8 low-order data bits when set as a separate bus.

P1

I/O port

P10 to P17

I/O

This is an 8-bit I/O port equivalent to P0.

Data bus

D8 to D15

I/O

These pins input and output 8 high-order data bits when set as a separate bus.

P2

I/O port

P20 to P27

I/O

This is an 8-bit I/O port equivalent to P0.

Address bus

A0 to A7

O

These pins output 8 low-order address bits.

P3

I/O port

P30 to P37

I/O

This is an 8-bit I/O port equivalent to P0.

Address bus

A8 to A15

O

These pins output 8 middle-order address bits.

P4

I/O port

P40 to P47

I/O

This is an 8-bit I/O port equivalent to P0.

Address bus

A16 to A 19

O

These pins output 4 high-order address bits.

Chip select

CS0 to CS3

OP44 to P47 are chip select output pins that specify access areas.

P5

I/O port

P50 to P57

I/O

This is an 8-bit I/O port equivalent to P0.

Bus control

WRL/WR

O

Ouput WRL, WRH (WR, BHE), and RD bus control signals. Using WRL and

WRH or WR and BHE can be switched using software control.

WRL, WRH, and RD selected.

WR, BHE, and RD selected.

Data is written when WR is "L". Data is read when RD is "L". Odd addresses are

accessed when BHE is "L". Use this mode when using an 8-bit external data bus.

WRH/BHE

O

RD

O

BCLK

O

Output operation clock for the CPU.

HOLD

I

While the HOLD pin input is "L", the MCU is placed in the Hold state.

HLDA

O

The HLDA pin output is "L" while the MCU is in the hold state.

ALE

O

The ALE pin can be used to latch the address.

RDY

I

While the RDY pin input is "L", the MCU is in the ready state.

AND Flash control

AND_SC

AND_WE

AND_OE

O

Control signal pins for communicating with AND type flash memory devices

AND Flash control

AND_DATA0 to 7

I/O

Data pins for communicating with AND type flash memory devices

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