R1Q4A3636B/R1Q4A3618B

REJ03C0343-0003 Rev.0.03 Apr.11, 2008

page 7 of 24

2b. Sequence controlled by Clock (/DOFF pin fixed high) when DLL enable

Status

Power Up

Unstable

Clock Stage

Stop

Clock Stage

NOP & DLL

Locking Stage

Normal

Operation

K, /K

C, /C,

30ns min.

1024cycle min.

/DOFF

DLL Constraints

1. DLL uses either K or C clock as its synchronizing input, the input should have low phase jitter which is specified as

TKC var.

2. The lower end of the frequency at which the DLL can operate is 119MHz.

Programmable Output Impedance

The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance

matching with a tolerance of 10% is 250

Ω typical. The total external capacitance of ZQ ball must be less than 7.5

pF.

Burst Sequence

Linear Burst Sequence Table (R1Q4A3636B / R1Q4A3618B series )

SA0

SA0

Notes

External address

0

1

1st internal burst address

1

0