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M38264M5AXXXFP Datasheet(PDF) 11 Page - Renesas Technology Corp |
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M38264M5AXXXFP Datasheet(HTML) 11 Page - Renesas Technology Corp |
11 / 93 page Rev.2.00 May. 24, 2006 page 11 of 90 REJ03B0028-0200 3826 Group (A version) [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit and the system clock control bits, etc. The CPU mode register is allocated at address 003B16. Fig. 8 Structure of CPU mode register Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : 1 1 : Stack page selection bit 0 : 0 page 1 : 1 page Not used (“1” at reading) (Write “1” to this bit at writing) XC switch bit 0 : Oscillation stop 1 : XCIN–XCOUT oscillating function Main clock (XIN–XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bit 0 : f(XIN)/2 (high-speed mode) 1 : f(XIN)/8 (middle-speed mode) System clock selection bit 0 : XIN–XOUT selected (middle-/high-speed mode) 1 : XCIN–XCOUT selected (low-speed mode) Do not select CPU mode register (CPUM (CM) : address 003B16) b7 b0 1 |
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