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M38039GCHHP Datasheet(PDF) 11 Page - Renesas Technology Corp |
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M38039GCHHP Datasheet(HTML) 11 Page - Renesas Technology Corp |
11 / 92 page Rev.1.10 Nov 14, 2005 Page 11 of 91 REJ03B0166-0110 3803 Group (Spec.H QzROM version) PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Fig 7. Register push and pop at interrupt generation and subroutine call Interrupt request (Note) M(S) ←(PCH) (S) ←(S) − 1 M(S) ←(PCL) ( S) ←(S) − 1 Execute RTS Subroutine (S) ←(S) + 1 (PCL) ←M(S) (S) ←(S) + 1 (PCH) ←M(S) M(S) ←(PCH) (S) ←(S) − 1 M(S) ←(PCL) (S) ←(S) − 1 M(S) ←(PS) (S) ←(S) − 1 Interrupt Service Routine (S) ←(S) + 1 (PS) ←M(S) (S) ←(S) + 1 (PCL) ←M(S) (S) ←(S) + 1 (PCH) ←M(S) Execute JSR Execute RTI Push Return Address on Stack Push Contents of Processor Status Register on Stack I Flag is Set from “0” to “1” Fetch the Jump Vector POP Contents of Processor Status Register from Stack POP Return Address from Stack POP Return Address from Stack Push Return Address on Stack Note : Condition for acceptance of an interrupt → Interrupt enable flag is “1” Interrupt disable flag is “0” On-going Routine Table 6 Push and pop instructions of accumulator or processor status register Push instruction to stack Pop instruction from stack Accumulator PHA PLA Processor status register PHP PLP |
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