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M306N4FCVGP Datasheet(PDF) 3 Page - Renesas Technology Corp |
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M306N4FCVGP Datasheet(HTML) 3 Page - Renesas Technology Corp |
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3 / 92 page  Rev.2.40 Aug 25, 2006 page 3 of 88 REJ03B0003-0240 M16C/6N Group (M16C/6N4) 1. Overview Under development This document is under development and its contents are subject to change. 1.3 Block Diagram Figure 1.1 shows a Block Diagram. Figure 1.1 Block Diagram NOTES: 1: ROM size depends on MCU type. 2: RAM size depends on MCU type. Timer (16 bits) Output (timer A): 5 Input (timer B): 6 Three-phase motor control circuit Internal peripheral functions Watchdog timer (15 bits) A/D converter (10 bits ✕ 8 channels Expandable up to 26 channels) UART or Clock synchronous serial I/O (3 channels) System clock generation circuit XIN-XOUT XCIN-XCOUT PLL frequency synthesizer On-chip oscillator Port P0 8 Port P1 8 Port P2 8 8 8 8 Port P6 8 Port P5 Port P4 Port P3 CRC calculation circuit (CCITT) (Polynomial: X 16+X12+X5+1) Clock synchronous serial I/O (8 bits ✕ 1 channel) CAN module (2 channels) DMAC (2 channels) D/A converter (8 bits ✕ 2 channels) Memory M16C/60 Series CPU core R0H R0L R1H R1L R2 R3 A0 A1 FB Multiplier INTB PC USP ISP SB FLG ROM (1) RAM (2) |
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