Rev.4.00 Apr 07, 2006 page 1 of 8

HD74SSTV32852

24-bit to 48-bit Registered Buffer with SSTL_2 Inputs and Outputs

REJ03D0833-0400

(Previous: ADE-205-687C)

Rev.4.00

Apr 07, 2006

Description

The HD74SSTV32852 is a 24-bit to 48-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS

reset (

RESET) input / SSTL_2 data (D) inputs and CLK input.

Data flow from D to QA, QB is controlled by differential clock pins (CLK,

CLK) and the RESET. Data is triggered on

the positive edge of the positive clock (CLK), and the negative clock (

CLK) must be used to maintain noise margins.

When

RESET is low, all registers are reset and all outputs are low.

To ensure defined outputs from the register before a stable clock has been supplied,

RESET must be held in the low

state during power up.

Features

• Supports LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input

• Differential SSTL_2 (Stub series terminated logic) CLK signal

• Pinout optimizes DIMM PCB layout

• Ordering Information

Part Name

Package Type

Package Code

(Previous code)

Package

Abbreviation

Taping Abbreviation

(Quantity)

HD74SSTV32852LBEL

LFBGA-114pin

PLBG0114GA-A

(BP-114V)

LB

EL (1,000 pcs / Reel)

Function Table

Inputs

Outputs

CLK

CLK

D

QA

QB

L

X or floating

X or floating

X or floating

L

L

H

↓

↑

H

H

H

H

↓

↑

L

L

L

H

L or H

H or L

X

*1

*1

H :

High level

L :

Low level

X :

Immaterial

↑ :

Low to high transition

↓ :

High to low transition

Notes: 1. Output level before the indicated steady state input conditions were established.

2. See under the figure.