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PSD835G3-B-70UI Datasheet(PDF) 10 Page - STMicroelectronics |
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PSD835G3-B-70UI Datasheet(HTML) 10 Page - STMicroelectronics |
10 / 110 page PSD835G2 PSD8XX Family Pin* (TQFP Pin Name Pkg.) Type Description PA0-PA7 51-58 I/O Port A, PA0-7. This port is pin configurable and has multiple CMOS functions: or Open 1. MCU I/O — standard output or input port Drain 2. CPLD Micro ⇔Cell (MCell A0-7) output. 3. Latched, transparent or registered PLD input. PB0-PB7 61-68 I/O Port B, PB0-7. This port is pin configurable and has multiple CMOS functions: or Open 1. MCU I/O — standard output or input port. Drain 2. CPLD Micro ⇔Cell (MCell B0-7) output. 3. Latched, transparent or registered PLD input. PC0-PC7 41-48 I/O Port C, PC0-7. This port is pin configurable and has multiple CMOS functions: or Slew 1. MCU I/O — standard output or input port. Rate 2. External chip select (ECS0-7) output. 3. Latched, transparent or registered PLD input. PD0 79 I/O Port D pin PD0 can be configured as: CMOS 1. ALE or AS input — latches addresses on ADIO0-15 pins or Open 2. AS input — latches addresses on ADIO0-15 pins on the Drain rising edge. 3. Input to the PLD. 4. Transparent PLD input. PD1 80 I/O Port D pin PD1 can be configured as: CMOS 1. MCU I/O or Open 2. Input to the PLD. Drain 3. CLKIN clock input — clock input to the CPLD Micro ⇔Cells, the APD power down counter and CPLD AND Array. PD2 1 I/O Port D pin PD2 can be configured as: CMOS 1. MCU I/O or Open 2. Input to the PLD. Drain 3. CSI input — chip select input. When low, the CSI enables the internal PSD memories and I/O. When high, the internal memories are disabled to conserve power. CSI trailing edge can get the part out of power-down mode. PD3 2 I/O Port D pin PD3 can be configured as: CMOS 1. MCU I/O or Open 2. Input to the PLD. Drain PE0 71 I/O Port E, PE0. This port is pin configurable and has multiple CMOS functions: or Open 1. MCU I/O — standard output or input port. Drain 2. Latched address output. 3. TMS input for JTAG/ISP interface. PE1 72 I/O Port E, PE1. This port is pin configurable and has multiple CMOS functions: or Open 1. MCU I/O — standard output or input port. Drain 2. Latched address output. 3. TCK input for JTAG/ISP interface (Schmidt Trigger). PE2 73 I/O Port E, PE2. This port is pin configurable and has multiple CMOS functions: or Open 1. MCU I/O — standard output or input port. Drain 2. Latched address output. 3. TDI input for JTAG/ISP interface. Table 5. PSD835G2 Pin Descriptions (cont.) 9 |
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