Rev.2.00 Jun. 28, 2004 page 1 of 13

HD74LV595A

8-bit Shift Registers with 3-state Outputs

REJ03D0335–0200Z

(Previous ADE-205-281 (Z))

Rev.2.00

Jun. 28, 2004

Description

This device each contains an 8-bit serial-in, parallel-out shift registers that feeds an 8-bit D-type storage register. The

storage register has parallel 3-state outputs. Separate clocks are provided for both the shift register and the storage

register. The shift register has a direct-overriding clear, serial input, and serial output pins for cascading.

Both the shift register and the storage register clocks are positive-edge triggered. If the user wishes to connect both

clocks together, the shift register state will always be one clock pulse ahead of the storage register. Low-voltage and

high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power

consumption extends the battery life.

Features

• V

• All inputs V

• All outputs V

• Typical V

• Typical V

• Output current ±6 mA (@V

• Ordering Information

Part Name

Package Type

Package Code

Package

Abbreviation

Taping Abbreviation

(Quantity)

HD74LV595AFPEL

SOP–16 pin (JEITA)

FP–16DAV

FP

EL (2,000 pcs/reel)

HD74LV595ARPEL

SOP–16 pin (JEDEC)

FP–16DNV

RP

EL (2,500 pcs/reel)

HD74LV595ATELL

TSSOP–16 pin

TTP–16DAV

T

ELL (2,000 pcs/reel)

Note: Please consult the sales office for the above package availability.

Function Table

Inputs

SER

SRCLK

SRCLR

RCLK

G

Function

XXXXH

Force outputs into high-impedance state

XXXXL

Enable parallel output

X

X

L

X

X

Reset shift register

L

↑

H

X

X

Shift data into shift register

H

↑

H

X

X

Shift data into shift register

X

↓

H

X

X

Shift register remains unchanged

XXX

↑

X

Transfer shift register contents to latch register

XXX

↓

X

Latch register remains unchanged

Note:

H: High level

L: Low level

X: Immaterial

↑: Low to high transition

↓: High to low transition