MOSEL VITELIC

V827464N24S

9

V827464N24S Rev. 1.0 August 2002

Detailed test conditions for DDR SDRAM IDD1 & IDD

IDD1 : Operating current: One bank operation

1. Typical Case : Vdd = 2.5V, T=25’ C

2. Worst Case : Vdd = 2.7V, T= 10’ C

3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once

per clock cycle. lout = 0mA

4. Timing patterns

- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK

Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing

*50% of data changing at every burst

- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK

Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing

*50% of data changing at every burst

- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK

Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing

*50% of data changing at every burst

Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP

Symbol

A1

PC1600@CL2

B0

PC2100B@CL2.5

B1

PC2100A@CL2

C0

PC2700@CL2.5

Unit

IDD0

1640

1860

1860

1990

mA

IDD1

1860

2180

2180

2540

mA

IDD2P

280

380

380

460

mA

IDD2F

640

640

640

280

mA

IDD2Q

640

740

740

190

mA

IDD3P

280

380

380

370

mA

IDD3N

1100

1280

1280

550

mA

IDD4R

2700

3440

3440

1700

mA

IDD4W

2360

3080

3080

1600

mA

IDD5

3260

3440

3440

1800

mA

IDD6

Normal

54

54

54

30

mA

Low power

33

33

33

33

mA

IDD7

4600

5400

5400

6400

mA